The present disclosure relates to the formation of capacitors in integrated circuits and, more specifically, the formation of non-single-crystalline-plated capacitors in integrated circuits. As used herein, non-single-crystalline material includes polycrystalline, amorphous and/or alloys of, for example, silicon and germanium. It specifically excludes metals.
Presently, polycrystalline-plated capacitors have been integrated in integrated circuits with field effect transistors (FETs), specifically, MOS FETs. Such a structure is illustrated in FIG. 1 and made by the general process of FIGS. 1–3 to be discussed below. Generally, the polycrystalline layer used to form the gate of the MOS transistors is also used to form the bottom plate of the polycrystalline capacitor. Typically, the bottom plate is patterned first and left exposed. Thus, its upper surface is exposed to various cleaning and photo-resist steps in the process flow. Also, the dielectric layer or layers used to form the dielectric of the capacitor is also exposed to various cleaning and photo-resist operations. The roughening of the surface of the first polycrystalline layer's upper surface, as well as the surface of the dielectric of the capacitor, effects the ultimate yield of the number of acceptable structures.
It has been suggested to use several dielectric layers, such as silicon dioxide and combinations of silicon and nitride, to protect the top surface of the bottom plate or first dielectric plate. This adds expense to the process.
Another limitation on the formation of the polycrystalline plate capacitor of FIG. 1 is the formation of stringers, which are regions of unetched polycrystalline material left adjacent to side walls of bottom plate steps which can result in unintended connections between polycrystalline structures. This results from the second polycrystalline layer conforming to steps in the first polycrystalline layer due to pre-patterning of the first layer making the second layer difficult to clear. To minimize the formation of stringers, the etching process to remove the top polycrystalline layer and form the top plate must be performed considerably longer than would be necessary for a planar layer in order to remove the additional polycrystalline thickness at the edges of the patterned or defined first polycrystalline plate. This additional etching also affects the surfaces that are subsequently exposed during the etching process. These include, for example, the surface dielectric covering the substrate in which the other elements of the integrated circuit, such as MOS FETs, are formed.
Metal plate capacitors have also been formed on integrated circuits. These capacitors have been formed at the interconnect level on the dielectric covering the elements of the integrated circuit. In this process, the bottom plate metallic layer, the capacitor dielectric layer and the top metal plate layer are formed. The top plate layer is then patterned, followed by patterning of the dielectric and the bottom plate layer. This process solves the problem of over-etching required by the step coverage. Also, because of the difference of materials, the etchings can be more selective to etch the metals versus the capacitor dielectric layer and the dielectric layer protecting the integrated circuit in a polycrystalline process. The physical displacement from the surface of the substrate in which integrated elements are formed also does not require the same care in the metal plate capacitor process as in the polycrystalline capacitor process. The capacitor is typically built on thicker field oxide, but the etch used to pattern the top layer attacks the substrate gate oxide extending from the edges of the MOS FETs, which is typically a thin insulative layer. This thin oxide is also the gate oxide and etch damage to it could adversely affect the performance of the MOS FETs, as well as the polycrystalline capacitors.
The present disclosure is directed to a method of forming non-single-crystalline capacitor in an integrated circuit. It includes the steps of forming a first non-single-crystalline layer on a gate dielectric layer of a substrate of an integrated circuit. Next, a capacitor dielectric layer is formed on the first non-single-crystalline layer, and a second non-single-crystalline layer is formed on the capacitor dielectric layer. Portions of the second non-single-crystalline layer are removed to define a top plate of the capacitor. Portions of the capacitor dielectric layer are removed to define a dielectric of the capacitor. Also, portions of the first non-single-crystalline layer are removed to define the bottom plate of the capacitor. By forming all three layers of the capacitor sequentially, preferably without any other intervening process steps, the surfaces between the non-single-crystalline plate layers and the dielectric layer are as defect-free as possible.
Removing portions of the first non-single-crystalline layer also simultaneously defines a gate of a transistor of the integrated circuit. Removing portions of the various layers are performed using masks with openings and etching-exposed material through the openings. Various combinations of masks may be used to etch the three layers, including a common mask for the dielectric and one of the non-single-crystalline layers.
These and other aspects of the present disclosure will become apparent from the following detailed description of the disclosure, when considered in conjunction with accompanying drawings.